faculty

Christopher LeBlanc

Associate Professor
UNH Manchester professor Christopher LeBlanc
Contact
Christopher.LeBlanc@unh.edu
Manchester - 88 Commercial Street, 88 Commercial Street,
(603) 641-4323

faculty Bio

Christopher D. LeBlanc is currently the Department Chair and Associate Professor for the Department of Applied Engineering and Sciences at the University of New Hampshire Manchester campus. Prior to his faculty appointment he spent 16 years at International Business Machines (IBM) as an Analog Mixed Signal design engineer. Professor LeBlanc's areas of expertise are Very Large Scale Integrated (VLSI) circuit design, semiconductor physics, and Analog Mixed signal design. He is an active member and author in the Institute of Electrical and Electronic Engineers (IEEE) and American Society of Engineering Education (ASEE). Professor LeBlanc has published in conference proceedings and journals for both IEEE and ASEE in the areas of Analog Mixed Signal Circuit Design, Memory Architecture, Phased Locked Loops, Voltage Regulator Architecture, Radiation Tolerance for Application Specific Integrated Circuits (ASICs), Engineering Technology education, and accreditation. He is serving a two year as the Chair of the ASEE Engineering Technology Division (ETD) from 2021 to 2023.



Professor LeBlanc holds a Bachelor of Science degree in Electrical Engineering from the University of Massachusetts Amherst and Master of Science in Electrical Engineering degree from the University of Vermont.

Courses Taught

  • ET 421: Digital Electronics I Lab
  • ET 502: Measurement and Control Lab
  • ET 541: Electronic Devices
  • ET 542: Analog Electronics Lab
  • ET 671: Digital Systems Lab
  • ET 675: Electrical Technology Lab
  • ET 677: Analog Systems Lab
  • ET 680: Communications and Fields Lab
  • ET 788: Intro to DSP

Education

  • M.S., University of Vermont
  • B.S., University of Massachusetts - Lowell
  • B.S., University of Massachusetts - Amherst

Selected Publications

  • Tavares, T., Banker, S., LeBlanc, C., & Ferguson, J. (2019). Collaboration on Engineering Technology Capstone Projects with the UNH University Instrumentation Center. In American Society for Engineering Education Conference for Industry and Education Collaboration. New Orleans, Louisiana.

  • LeBlanc, C. (2019). Adopting the Cadence Design System for an Engineering Technology Program. In ASEE Conference of Industry and Education Collaboration. http://www.indiana.edu/~ciec/Proceedings_2019/ETD/ETD525_Leblanc.pdf.

  • Continuous Improvement of a 2+2 Engineering Technology Program a Ten Year Study (2017). Retrieved from http://www.asee.org/

  • Bulzacchelli, J. F., Toprak-Deniz, Z., Rasmus, T. M., Iadanza, J. A., Bucossi, W. L., Kim, S., . . . Friedman, D. J. (2012). Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(4), 863-874. doi:10.1109/JSSC.2012.2185354

  • Jin, K. H., Jonas, M., LeBlanc, C., & Tavares, T. S. (2018, June 24). Modernizing Capstone Project: External and Internal Approaches. In the 2018 ASEE the 125th Annual Conference & Exposition. Salt Lake City, Utah.

  • LeBlanc, C. (n.d.). Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage. In 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

  • Leblanc, C., Sabin, M., & Dundorf, C. (2017, June 24). An Engineering Technology Capstone Project: The Snow Load Network. In 2017 ASEE Annual Conference & Exposition Proceedings. ASEE Conferences. doi:10.18260/1-2--27556

  • LeBlanc, C., Uddin, M., Johnson, K., & Rogers, P. (2019, June 15). Pedagogical Risk Taking: Is it worth it?. In American Society of Engineering Education National Conference. Tampa Florida.

  • LeBlanc, C., Plante, D., & LeBlanc, C. D. (2018, June 23). An Engineering Technology Course in Additive Manufacturing. In American Society of Engineering Educators. Salt Lake City Utah.

  • LeBlanc, C. (n.d.). A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. In 2007 IEEE Custom Integrated Circuits Conference.